Electrically erasable memory cells are nowadays widely used in many applications. Among these, Flash cells are of particular importance since they can be easily scaled with technologies that, for the future, will move to channel lengths of 90 nm and less.
In this context it becomes more and more important to succeed in integrating these types of Flash cells in standard CMOS technologies, so as to obtain memories of the embedded type which are nowadays widely used in many fields of the semiconductor market, such as SIM modules or memories for automotive applications.
When Flash memory cells are to be integrated in the recent 90 nm CMOS technologies there arise problems linked to the need, for low voltage transistors (or LV transistors), for operating with lower and lower supply voltages. The voltages supplied externally do not scale in the same way but tend to remain rather high, making it necessary to use Voltage Down Converters.
If these converters allow the separation of an external supply reference from an internal one, in correspondence with the current absorption peaks of, for example, an internal circuit of a memory device, they are subjected to inevitable losses or drops which can be on the order of some hundreds of mV. In this way, although using a converter suitable for regulating an internal supply voltage reference at a value for example equal to 1.2V (a typical working voltage for transistors realized in 90 nm technologies), it is inevitable that, due to this drop phenomenon, in reality minimum voltage values are obtained that can reach 1V.
All this implies significant difficulties in the design of memory devices, in particular of the Flash type, which normally need high operating voltages so as to modify and read the content of the memory cells.
Inside these memory devices of the Flash type a charge pump system is thus provided for the generation, starting from a single external supply voltage reference, of the internal voltage references that are necessary for the correct operation (e.g., reading, writing and erasing operations) of the Flash memory. This charge pump system is one of the analog blocks that is most difficult to implement and has to meet the following specifications:
1) minimum area occupation,
2) reduced current consumption,
3) functionality at very low supply voltage values, and
4) simultaneous generation of positive and negative voltage values with different regulation levels (in particular equal to +5V, +10V, and −10V).
Further problems arise in particular applications that provide wide external supply voltage ranges. This is the case, for example, in Smart Card applications, where the range of external supply voltage is extremely wide (from 1.65V up to 5.5V).
In these applications, the design of the charge pump system, normally supplied directly with these external supply voltages, turns out to be extremely complicated due to the wide range, which impels to:
a) use, in any case, many charge pump stages (normally also indicated as pumping phases) inside this charge pump system, in cascade to each other and with pump capacitors of great capacitance for meeting a lower limit of the external supply voltage range (normally equal to 1.65V);
b) insert some extremely large filter capacitors for reducing the ripple in correspondence with the high values of the external supply voltage range (normally equal to 5.5V); and
c) entirely design the charge pump system with high voltage transistors (or HV transistors), with the buffer stages of the charge pump stages included, with a subsequent increase in the silicon area occupied by the system as a whole.
Normally, in Flash memories, it is necessary to generate at least three different regulated voltages so as to manage the operations of:
1) reading, in this case, the charge pump system must supply a first reading voltage Vr (normally equal to +5V);
2) programming, in this case, the charge pump system must simultaneously supply a first Vp1 and a second Vp2 programming voltage (normally equal to +5V, +10V, and −1V), the negative voltage value being in particular used for biasing, during a programming operation, the non-selected wordlines; and
3) erasing, in this case, the charge pump system must simultaneously supply a first Ve1 and a second Ve2 erasing voltage (normally equal to +10V, and −10V).
Since the required reading voltage is equal to the first programming voltage (Vr=Vp1), and the required second programming voltage is equal to the first erasing voltage (Vp2=Ve1), the charge pump system will practically have to supply three working voltages, usually indicated with VXR, VYP, and VNEG, and having values equal to +5V, +10V, and −10V, respectively.
A known charge pump system is shown in FIG. 1. The charge pump system 1 comprises, in particular, a first 2, a second 3, and a third 4 pump, all supplied by the same internal supply voltage reference Vdd and suitable for supplying, on respective output terminals O2-O4 the above indicated working voltages. The pumps 2-4 are realized in a known way by a cascade of N charge pump stages.
It is possible to distinguish between the following cases:
a) the internal supply voltage Vdd is taken by a Voltage Down Converter and has a minimum voltage value equal to a minimum external supply voltage value (equal for example to 1.65V) further decreased by a fall or drop value (an inevitable drop being the Voltage Down Converter, a non-ideal element, normally equal to ˜200 mV); in the indicated example, the internal supply voltage value Vdd is thus equal to ˜1.45V; and
b) the internal supply voltage Vdd coincides with one of the LV circuits in the Flash memory device and thus reaches a minimum value which can be also reduced below 1V.
In the first case, the three pumps 2, 3, and 4 of the system 1 should be completely realized with HV transistors, with a consequent large use of silicon area due to the rules used and to the lower efficiency of HV transistors with respect to LV transistors. Moreover, the frequency of use will not be very high (˜60 MHz).
In the second case, the first 2 and the second 3 pumps (i.e., the pumps generating positive voltages) can be realized by LV transistors and HV capacitors so as to allow a savings in area with respect to the first case, and only the third pump 3 (i.e., the pump generating a negative voltage) has to be realized with HV transistors and capacitors. However, considering the ratio between the working voltage to be generated (+/−10V) and the internal supply voltage Vdd (+1V), they should comprise a high number N of pump stages (about N3=18 stages for the second pump 3 and up to N4=20 stages for the third pump 4, as indicated in the figure, in the case of an internal supply voltage Vdd equal to 1V).